• Name (Pinyin):
  chenjiezhi
• Date of Employment:
  2016-07-01
• School/Department:
  School of Information Science and Engineering, Shandong University
• Administrative Position:
  Professor
• Education Level:
  With Certificate of Graduation for Doctorate Study
• Business Address:
  N5 Building, Binghai Road #72, Jimo, Qingdao, 266237, China
• Gender:
  Male
• Contact Information:
  chen.jiezhi@sdu.edu.cn
• Degree:
  Doctor
• Status:
  Employed
• Alma Mater:
  University of Tokyo
• Supervisor of Doctorate Candidates
• Supervisor of Master's Candidates

Jiezhi Chen (Senior Member, IEEE) received the Ph.D. degree from the Department of Informatics and Electronics, University of Tokyo, Tokyo, Japan, in 2009. In 2010, he joined the R&D Center, Toshiba Corporation, Tokyo. He is currently a Professor with the School of Information Science and Engineering, Shandong University, Jinan, China. He has published many articles in journals and conference proceedings and acted as a reviewer of several international journals. His work on nanoscale devices and device reliabilities has been the leading author or the corresponding author for more than ten times in VLSI Symposium and IEEE International Electron Device Meeting (IEEE IEDM) since 2008. His research interests include the characterization and process engineering of nano-scale transistors and nonvolatile memories, with main focus on reliability physics.,Dr. Chen serves as a Technical Program Committee (TPC) Member for IEDM (2016-2017, 2022-2023), and has been a TPC Member of Silicon Nanoelectronics Workshop since 2018, the IEEE International Reliability Physics Symposium since 2019, and the IEEE International Memory Workshop since 2020.

【Publications in IEDM & VLSI Symposia】

• "Temperature-dependent Defect Behaviors in Ferroelectric Hf0.5Zr0.5O2 Thin Film:  Re-wakeup Phenomenon and Underlying Mechanisms,"

  2022 IEDM Tech. Dig., 32.3.1-4;

• "Design-Technology Co-Optimizations (DTCO) for General-Purpose In-Memory Computation Based on 55nm NOR Flash Technology"

  2021 IEDM Tech. Dig., 12.1.1-4; 

•  "In-depth Understanding of Polarization Switching Kinetics in Polycrystalline Hf0.5Zr0.5O2 Ferroelectric Thin Film: A Transition from NLS to KAI,"

  2021 IEDM Tech. Dig., 19.1.1-4;

• "Two-Dimensional Silicon Atomic Layer Field-Effect Transistors: Electronic Property, Metal-Semiconductor Contact, and Device Performance,"

  2021 IEDM Tech. Dig., 27.2.1-4;

• “Deep Insights into the Failure Mechanisms in Field-cycled Ferroelectric Hf0.5Zr0.5O2 Thin Film: TDDB Characterizations and First-Principles Calculations”

  2020 IEDM Tech. Dig., 39.6.1-4;

•  “Cold Source Engineering towards Sub-60mV/dec p-Type Field-effect-transistors (pFETs): Materials, Structures, and Doping Optimizations”

  2020 IEDM Tech. Dig., 22.4.1-4;

•  “Computational Design of Silicon Contacts on 2D Transition-Metal Dichalcogenides: The Roles of Crystalline Orientation, Doping Level, Passivation and Interfacial layer"

  2018 IEDM Tech. Dig., 21.2.1-4;

•  “A low-power and high-speed True Random Number Generator using generated RTN,”

  2018 Symposia on VLSI Technology, pp.95-96;

• “Comprehensive Investigations on Charge Diffusion Physics in SiN-based 3D NAND Flash Memory through Systematical Ab initio Calculations"

  2017 IEDM Tech. Dig., 4.5.1-4;

• “Deep Insight into Process-induced Pre-existing Traps and PBTI Stress-induced Trap Generations in High-k Gate Dielectrics through Systematic RTN Characterizations and Ab initio Calculations,”

  2016 Symposia on VLSI Technology;

• “Further Investigations on Traps Stabilities in Random Telegraph Signal Noise and the Application to a Novel Concept Physical Unclonable Function (PUF) with Robust Reliabilities,”

  2015 Symposia on VLSI Technology;

• “Further Understandings on Random Telegraph Signal Noise through Comprehensive Studies on Large Time Constant Variations and its Strong Correlations to Thermal Activation Energies,”

  2014 Symposia on VLSI Technology;

•  “Understanding of Channel Doping Concentration Impacts on Random Telegraph Signal Noise and Successful Noise Suppression from Strain Induced Mobility Enhancement,”

  2013 Symposia on VLSI Technology;

• “Comprehensive Investigations on Neutral and Attractive Traps in Random Telegraph Signal Noise Phenomena using (100)- and (110)-Orientated CMOSFETs,” 

  2012 Symposia on VLSI Technology;

• “Mobility enhancement over universal mobility in (100) silicon nanowire gate-all-around MOSFETs with width and height of less than 10nm range,”

  2010 Symposia on VLSI Technology;

•  “High Hole Mobility in Multiple Silicon Nanowire Gate-All-Around pMOSFETs on (110) SOI,”

  2009 Symposia on VLSI Technology;

• ”Experimental Study of Mobility in [110]- and [100]-Directed Multiple Silicon Nanowire GAA MOSFETs on (100) SOI,”

  2008 Symposia on VLSI Technology;

•  “Electron Mobility in Multiple Silicon Nanowires GAA nMOSFETs on (110) and (100) SOI at Room and Low Temperature,”

  2008 IEDM Tech. Dig., p.761-764