Jiezhi Chen (Senior Member, IEEE) received the Ph.D. degree from the Department of Informatics and Electronics, University of Tokyo, Tokyo, Japan, in 2009. In 2010, he joined the R&D Center, Toshiba Corporation, Tokyo. He is currently a Professor with the School of Information Science and Engineering, Shandong University, Jinan, China. He has published many articles in journals and conference proceedings and acted as a reviewer of several international journals. His work on nanoscale devices and device reliabilities has been the leading author or the corresponding author for more than ten times in VLSI Symposium and IEEE International Electron Device Meeting (IEEE IEDM) since 2008. His research interests include the characterization and process engineering of nano-scale transistors and nonvolatile memories, with main focus on reliability physics.,Dr. Chen serves as a Technical Program Committee (TPC) Member for IEDM (2016-2017, 2022-2023), and has been a TPC Member of Silicon Nanoelectronics Workshop since 2018, the IEEE International Reliability Physics Symposium since 2019, and the IEEE International Memory Workshop since 2020.
【Publications in IEDM & VLSI Symposia】
"Temperature-dependent Defect Behaviors in Ferroelectric Hf0.5Zr0.5O2 Thin Film: Re-wakeup Phenomenon and Underlying Mechanisms,"
2022 IEDM Tech. Dig., 32.3.1-4;
"Design-Technology Co-Optimizations (DTCO) for General-Purpose In-Memory Computation Based on 55nm NOR Flash Technology"
2021 IEDM Tech. Dig., 12.1.1-4;
"In-depth Understanding of Polarization Switching Kinetics in Polycrystalline Hf0.5Zr0.5O2 Ferroelectric Thin Film: A Transition from NLS to KAI,"
2021 IEDM Tech. Dig., 19.1.1-4;
"Two-Dimensional Silicon Atomic Layer Field-Effect Transistors: Electronic Property, Metal-Semiconductor Contact, and Device Performance,"
2021 IEDM Tech. Dig., 27.2.1-4;
“Deep Insights into the Failure Mechanisms in Field-cycled Ferroelectric Hf0.5Zr0.5O2 Thin Film: TDDB Characterizations and First-Principles Calculations”
2020 IEDM Tech. Dig., 39.6.1-4;
“Cold Source Engineering towards Sub-60mV/dec p-Type Field-effect-transistors (pFETs): Materials, Structures, and Doping Optimizations”
2020 IEDM Tech. Dig., 22.4.1-4;
“Computational Design of Silicon Contacts on 2D Transition-Metal Dichalcogenides: The Roles of Crystalline Orientation, Doping Level, Passivation and Interfacial layer"
2018 IEDM Tech. Dig., 21.2.1-4;
“A low-power and high-speed True Random Number Generator using generated RTN,”
2018 Symposia on VLSI Technology, pp.95-96;
“Comprehensive Investigations on Charge Diffusion Physics in SiN-based 3D NAND Flash Memory through Systematical Ab initio Calculations"
2017 IEDM Tech. Dig., 4.5.1-4;
“Deep Insight into Process-induced Pre-existing Traps and PBTI Stress-induced Trap Generations in High-k Gate Dielectrics through Systematic RTN Characterizations and Ab initio Calculations,”
2016 Symposia on VLSI Technology;
“Further Investigations on Traps Stabilities in Random Telegraph Signal Noise and the Application to a Novel Concept Physical Unclonable Function (PUF) with Robust Reliabilities,”
2015 Symposia on VLSI Technology;
“Further Understandings on Random Telegraph Signal Noise through Comprehensive Studies on Large Time Constant Variations and its Strong Correlations to Thermal Activation Energies,”
2014 Symposia on VLSI Technology;
“Understanding of Channel Doping Concentration Impacts on Random Telegraph Signal Noise and Successful Noise Suppression from Strain Induced Mobility Enhancement,”
2013 Symposia on VLSI Technology;
“Comprehensive Investigations on Neutral and Attractive Traps in Random Telegraph Signal Noise Phenomena using (100)- and (110)-Orientated CMOSFETs,”
2012 Symposia on VLSI Technology;
“Mobility enhancement over universal mobility in (100) silicon nanowire gate-all-around MOSFETs with width and height of less than 10nm range,”
2010 Symposia on VLSI Technology;
“High Hole Mobility in Multiple Silicon Nanowire Gate-All-Around pMOSFETs on (110) SOI,”
2009 Symposia on VLSI Technology;
”Experimental Study of Mobility in [110]- and [100]-Directed Multiple Silicon Nanowire GAA MOSFETs on (100) SOI,”
2008 Symposia on VLSI Technology;
“Electron Mobility in Multiple Silicon Nanowires GAA nMOSFETs on (110) and (100) SOI at Room and Low Temperature,”
2008 IEDM Tech. Dig., p.761-764
Micro/Nano Device Reliability Lab.(DRL) is a laboratory aiming at micro/nano-scale transistors and non-volatile memorise with three-dimensional (3D) architectures.The mian target is to extend "More Moore" teachnology with focus on the robust reliability desgin and to link “More Moore" with“Beyond CMOS" by defects engineering between traditonal materials and new concept materials.
3D NAND Flash Memory
Emerging Non-Volatile Memory
Low-Power(LP) nano-scale FET
New Concept Device and Materials
In-Memory Computing (IMC) DTCO
Publications in Journals
[1] D. Zhang, H. Wang, Y. Feng, X. Zhan, J. Chen*, J. Liu*, M. Liu, Implementation of Image Compression by Using High-Precision In-Memory Computing Scheme Based on NOR Flash Memory, IEEE Electron device letters, 2021
[2] F. Chen, B. Chen, H. Lin, Y. Kong, X. Liu, X. Zhan, J. Chen*, Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories, 12, 1152, 2021.
[3] P. Sang, Q. Wang, W. Wei, F. Wang, Y. Li*, J. Chen*, Semiconducting Silicene: A Two-Dimensional Silicon Allotrope with Hybrid Honeycomb-Kagome Lattice，ACS Materials Lett. 3, 8, 1181–1188, 2021 (cover)
[4] Q. Wang, P. Sang, F. Wang, W. Wei, J. Chen*, Tunneling Junction as Cold Source: Toward Steep-Slope Field-Effect Transistors Based on Monolayer MoS2, IEEE TED, 68(9), p.4758, 2021.
[5] Q. Wang, P. Sang, F. Wang, W. Wei, Y. Li, J. Chen*, Strain engineered C31 field-effect-transistors: a new strategy to break 60mV/decade by using electron injection from intrinsic isolated states, APEX, 14, p.074003, 2021.
[6] X. Zhan, G. Zhao, X. Yu, B. Chen, J. Chen, “Digital and analog functionality in monolayer AlOx-based memristors with various oxidizer sources”, Nanotechnology, 35LT01, 2021;
[7] P. Sang, X. Ma, Q. Wang, W. Wei, F. Wang, J. Wu, X. Zhan, Y. Li*, J. Chen*, Toward high-performance monolayer graphdiyne transistor: Strain engineering matters, Applied Surface Science, 536, p.147836, 2021.
[8] F. Wang, Y. Li, X. Ma, J. Chen, “Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory”, IEEE Access, 9, 47391, 2021;
[9] Zheng Zhou, Jiawei Wang*, Jiezhi Chen*, Chao Jiang, Ling Li*, Ming Liu, “Directly probing the charge transport in initial molecular layers of organic polycrystalline field effect transistors”, Journal of Materials Chemistry C, 9, 649-656, 2021
[10] Y. Feng, F. Wang, X. Zhan, Y. Li, J. Chen*, “Flash Memory based Computing-in-memory system to Solve Partial Differential Equations”, Sci. China Inf. Sci., 64, 169401, 2021;
[11] P. Sang, X. Ma, Q. Wang, W. Wei, F. Wang, J. Wu, X Zhan, Y Li*, J. Chen*, “Toward high-performance monolayer graphdiyne transistor: Strain engineering matters”, Applied Surface Science, Vol 536, 147836, Jan. 2021;
[12] Y. Kong, M. Zhang, X. Zhan, R. Cao, J. Chen*, “Retention Correlated Read Disturb Errors in 3-D Charge Trap NAND Flash Memory: Observations, Analysis, and Solutions”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 11, pp. 4042-4051, Nov. 2020;
[13] F. Wang, Y. Feng, X. Zhan, B. Chen*, J. Chen*, “Implementation of Data Search in Multi-level NAND Flash Memory by Complementary Storage Scheme”, IEEE Electron Device Letter, 41, 8, 1189, Aug. 2020;
[14] F. Lu, Q. Qin, Y. Li*, J. Chen*, “Computational design of molecular transistor with van der Waals gating”, Applied Physics Express, 13, 085002, Aug. 2020;
[15] X. Zhan, Y. Xi, Q, Wang, W. Zhang, Z. Ji, and J. Chen*, “Dual-Point Technique for Multi-Trap RTN Signal Extraction”, IEEE Access, 8, 88141, 2020;
[16] F. Wang, R. Cao, Y. Kong, X. Ma, X. Zhan, Y. Li, J. Chen*, “Lateral Charge Migration Induced Abnormal Read Disturb in 3D Charge-Trapping NAND Flash Memory”, Applied Physics Express, 13, 054002, May. 2020;
[17] Y. Li*, Y. Yi, B. Cui, J. Chen*, “Two-dimensional electronic and charge-transport properties of a monolayer organic crystal: Impacts of the collinear transfer-integral correlations”, Organic Electronics 78, 105609, 2020;
[18] F. Wang, J. Wu, Y. Li, R. Cao, J. Chen*, “Metallic doping: A new strategy for suppressing shallow-trap centers in vertically stacked charge-trapping flash memories”, Applied Physics Express, 13, 044001, Apr. 2020;
[19] X. Ma, F. Wang, W. Wei, J. Wu, X. Zhan, Y. Li, J. Chen*, “Impacts of Extra Charges on Trap Level Modulations at cSi/aSiO2 Interface: Correlations to Leakage Current Recovery in Oxide Dielectric”, J. Phys. D: Appl. Phys., 53, 245103, Jun. 2020;
[20] X. Ma, X. Jiang, Yuan Li, J. Chen*, “Schottky-barrier modulation at germanium/monolayer MoS2 heterojunction interface: the roles of passivation and interfacial layer”, Applied Physics Express,13, 021004, 2020
[21] X. Ma, Y. Gong, J. Wu, Y. Li, J. Chen*, “Impacts of atomistic surface roughness on electronic transport in n-type and p-type MoS2 field-effect transistors”, Jpn. J. Appl. Phys. 58 110905, 2019;
[22] W. Wei, X. Ma, J. Wu, F. Wang, X. Zhan, Y. Li, J. Chen*, “Spontaneous polarization enhancement in ferroelectric Hf0.5Zr0.5O2 using atomic oxygen defects engineering: an ab initio study”, Appl. Phy. Lett., 115, 092905, 2019;
[23] J. Wu, J. Chen*, X. Jiang*, “Multiscale simulation of lateral charge loss in Si3N4 3D NAND flash based on density functional theory”, J. Phys. D: Appl. Phys. 52, 395103, 2019;
[24] J. Wu, J. Chen*, X. Jiang*, “Atomistic Study of Lateral Charge Diffusion Degradation During Program/Erase Cycling in 3-D NAND Flash Memory”, IEEE Journal of the Electron Devices Society, vol.7,1, pp.626-631, 2019;
[25] J. Wu, X. Ma, J. Chen*, X. Jiang*, “Defects coupling impacts on mono-layer WSe2 tunneling field-effect transistors”, Applied Physics Express,12, 034001, 2019;
[26] X. Zhan, M. Hou, F. Ma, Y. Su, J. Chen*, H. Xu*, “Room temperature crystallization of amorphous silicon film by ultrashort femtosecond laser pulses”, Optics and Laser Technology 112 (2019), pp.363-367;
[27] Z. Fan, J. Chen* and X. Jiang*, “Electrical Contacts and Tunable Rectifications in Monolayer GeSe-Metal Junctions,” Journal of Physics D: Appl. Phys. 51 (2018) 335104;
[28] J. Lu, Z. Fan*, J. Gong*, J. Chen*, H. ManduLa, Y. Zhang, S. Yang and X. Jiang, “Enhancement of tunneling current in monolayer phosphorene tunnel field effect transistors by surface defects,” Physical Chemistry Chemical Physics, 20, pp.5699~5707, 2018.
[29] J. Wu, Z. Fan, J. Chen*, X. Jiang*, “Atomic defects in monolayer WSe2 tunneling FETs studied by systematic ab initio calculations,” Applied Physics Express,11, 054001, 2018
International Conferences
[1] Y. Feng, et al., Design-Technology Co-Optimizations (DTCO) for General-Purpose In-Memory Computation Based on 55nm NOR Flash Technology, IEDM 2021
[2] W. Wei, et al., In-depth Understanding of Polarization Switching Kinetics in Polycrystalline Hf0.5Zr0.5O2 Ferroelectric Thin Film: A Transition from NLS to KAI, IEDM 2021
[3] P. Sang, et al., Two-Dimensional Silicon Atomic Layer Field-Effect Transistors: Electronic Property, Metal-Semiconductor Contact, and Device Performance, IEDM 2021
[4] J. Chen, ASICON 2021, invited talk.
[5] Y. Xi, et al., Error Bits Mapping in Triple-level-cell (TLC) Charge-trap (CT) 3D NAND Flash Memory and its Applications to IoT Security, ICTA, 2021. Best paper
[6] Q. Jin, L. Cui, X. Zhan, J. Liu, J. Chen, “Variations of Bias Dependent Timing Constants and Its Implication on Trap Positions and Energy Levels by the Hidden Markov Model”, Silicon Nanoelectronics Workshop (SNW), Virtual, June, 2021;
[7] F. Lu, Y. Li, J. Chen, “Electronic Transport Across the Grain Boundary of Poly-Si Channel In 3D NAND Flash Memory: A Theoretical Perspective”, Silicon Nanoelectronics Workshop (SNW), Virtual, June, 2021;
[8] F. Wang, X. Ma, W. Wei, P. Sang, Q. Wang, W. Zhang, Y. Li, J. Chen, “Sub-3nm Transition-Metal Dichalcogenides FETs: Theoretical Insights into the Impacts of Layer Numbers and Channel Lengths”, IEEE Electron Devices Technology and Manufacturing (EDTM) conferences, April 8-11, 2021, Chengdu, China;
[9] X. Fang, Y. Kong, Y. Guo, M. Jia, X. Zhan, Y. Li, J. Chen, “Impacts of Operation Intervals on Program Disturb in 3D Charge-trapping Triple-level-cell (TLC) NAND Flash Memory”, IEEE Electron Devices Technology and Manufacturing (EDTM) conferences, April 8-11, 2021, Chengdu, China;
[10] W. Wei, W. Zhang, F. Wang, X. Ma, Q. Wang, P. Sang, X. Zhan, Y. Li, L. Tai, Q. Luo, H. Lv, J. Chen, “Deep Insights into the Failure Mechanisms in Field-cycled Ferroelectric Hf0.5Zr0.5O2 Thin Film: TDDB Characterizations and First-Principles Calculations”, IEDM Tech. Dig., virtual, p.39.6.1-39.6.4, 2020;
[11] Q. Wang, P. Sang, X. Ma, Y. Li, J. Chen., “Cold Source Engineering towards Sub-60mV/dec p-Type Field-effect-transistors (pFETs): Materials, Structures, and Doping Optimizations”, IEDM Tech. Dig., virtual, p.22.4.1-22.4.4, 2020;
[12] F. Wang, X. Zhan, Y. Li, J. Chen*, “Impacts of Poly-Si Channel on Cell Variations in Vertical Scaled Charge-trap (CT) 3D NAND Flash Memory”, the International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Nov.3-6, 2020, Kunming, China;
[13] X. Peng, F. Wang, Y. Kong, M. Jia, X. Zhan, Y. Li, J. Chen*, “Impacts of Lateral Charge Migration on Data Retention and Read Disturb in 3D Charge-trap NAND Flash Memory”, the International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Nov.3-6, 2020, Kunming, China;
[14] Y. Kong, X. Peng, F. Wang, M. Jia, X. Zhan, Y. Li, J. Chen*, “Comprehensive Investigations on Data Pattern Dependences in Charge-trap (CT) 3D NAND Flash Memory”, the International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Nov.3-6, 2020, Kunming, China;
[15] J. Chen* (invited), “Read Disturbs in Triple-Level-Cell 3D Charge-trap NAND Flash Memory”, the International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Nov.3-6, 2020, Kunming, China;
[16] Q. Qin, F. Wang, X. Zhan, Y. Li, J. Chen*, “TID Radiation Impacts on Charge-trapping Macaroni 3D NAND Flash Memory”, accepted by IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, July, 2020;
[17] Y. Feng, J. Chen*, “Flash Memory based Computing-In-Memory to Solve Time-dependent Partial Differential Equations”, Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, June, 2020;
[18] Q. Wang, P. Sang, Y. Li, W. Wei, F. Wang, J. Chen*, “Biaxial Tensile Strain Impacts on Monolayer WSe2 Tunneling Field-effect-transistor (TFET)”, Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, June, 2020;
[19] Y. Li, Q. Wang, X. Zhan, M. Jia, R. Cao, J. Chen*, “a Novel quasi-SLC(qSLC) Program/Erase Scheme in Ultra-Densified Charge-trapping 3D NAND Flash Memory to Enhance System Level Performance”, Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, June, 2020;
[20] X. Ma, R. Cao, F. Wang, X. Zhan, J. Chen*, “Charge-assisted Recovery and Degradation in Charge-trapping 3D NAND Flash Memory, Experimental Evidences and Theoretical Perspectives”, Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, June, 2020;
[21] F. Wang, X. Ma, J. Wu, J. Chen*, X. Jiang*, “Atomistic Study of Transport Characteristics in Sub-1nm Ultra-narrow Molybdenum Disulfide (MoS2) Nanoribbon Field Effect Transistors”, Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, June, 2019;
[22] J. Wu, J. Chen*, X. Jiang*, “Excess Charge Effects on Semiconductor-metal Phase Transition in Mono-layer MoTe2”, Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, June, 2019;
[23] R. Cao, J. Wu, W. Yang, J. Chen*, X. Jiang*, “Program/Erase Cycling Enhanced Lateral Charge Diffusion in Triple-level Cell Charge-trapping 3D NAND Flash Memory”, IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2019;
[24] X. Ma, Y. Liu, L. Wang, Y. En, J. Chen*, X. Jiang*, “Scaling behavior of state-to-state coupling during hole trapping at Si/SiO2”, IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2019;
[25] X. Ma, Z. Fan, J. Wu, X. Jiang*, J. Chen*, “Computational Design of Silicon Contacts on 2D Transition-Metal Dichalcogenides: The Roles of Crystalline Orientation, Doping Level, Passivation and Interfacial Layer”, IEDM Tech. Dig., San Francisco, CA, USA, p.24.2.1-24.2.4, 2018;
[26] X, Zhan, F. Ma, J. Chen*, Y. Li and H. Xu*, “Crystallizing amorphous silicon film by using femtosecond laser pulses,” 2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), pp.84-85, November 21- 23, 2018, Beijing, China;
[27] W. Yang, Y. Li, B. Wang, H. Qian and J. Chen*, “Positive Bias Temperature Instabilities in Vertical Gate-all-around poly-Si Nanowire Field-effect Transistor,” 2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), pp.175-176, November 21- 23, 2018, Beijing, China;
[28] J. Chen (invited), “On the Reliability of Charge-Trap (CT) Type Three-dimensional (3D) NAND Flash Memory,” invited talk in The 14th International Conference on Solid-State and Integrated Circuit Technology, October 31-November 3, 2018, Qingdao, China;
[29] R. Cao, J. Wu, W. Yang, Y. Li, J. Chen*, “Error Bit Distributions in Triple-level Cell Three-dimensional (3D) NAND Flash Memory,” the 14th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), October 31- November 3, 2018, Qingdao, China;
[30] F. Ma, X. Zhan, Y. Li, J. Chen*, “Numerical Simulations on Nanosecond Pulse Laser Annealing in Vertical Polycrystalline Si Macaroni Channel,” the International Conference on Solid-State and Integrated Circuit Technology (ICSICT), October 31- November 3, 2018, Qingdao, China;
[31] J. Brown, R. Gao, J. Crowford, J. Wu, Z. Ji*, J. Chen*, J. Zhang, B. Zhou, B. Zhou, Q. Shi, W. Zhang, “A low-power and high-speed True Random Number Generator using generated RTN”, Symposia on VLSI Technology, pp.95-96, Hawaii, USA, June, 2018;
[32] J. Wu, X. Ma, J. Chen*, X. Jiang*, “Se Vacancy Defects Coupling Effects in Mono-layer WSe2 Tunnel FETs”, Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, June, 2018;
[33] X. Ma, Z. Fan, J. Wu, J. Chen*, X. Jiang*, “Channel Bending Effects on On/Off Currents in Mono-Layer MoS2 FETs”, Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, June, 2018;
[34] W. Yang, J. Zhao, H. Cao, S. Chiu, J. Chen*, “Oxide-Nitride-Oxide(ONO) Inter-poly Dielectric (IPD) Scaling Impacts on Data Retention Characteristics in NAND Flash Memories”, Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, June, 2018;
[35] J. Wu, D. Han, W. Yang, S. Chen, X. Jiang*, J. Chen*, “Comprehensive Investigations on Charge Diffusion Physics in SiN-based 3D NAND Flash Memory through Systematical Ab initio Calculations,” IEDM Tech. Dig., San Francisco, CA, USA, p.4.5.1-4.5.4, 2017.
[36] J. Chen, J. Wu, X. Jiang, (invited) “Impacts of Traps on Nano Scale Device Performance, Reliability, and Novel Applications”, invited talk, in International Microprocesses and Nanotechnology Conference, JeJu, Korea, November, 2017;
[37] J. Wu, Z. Fan, J. Chen*, X. Jiang*, “A Study on W Vacancy Defect in Mono-layer Transition-Metal Dichalcogenide (TMD) TFETs through Systematic Ab initio Calculations”, Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, June, 2017;
[38] J. Chen, Y. Nakasaki and Y. Mitani. “Deep Insight into Process-induced Pre-existing Traps and PBTI Stress-induced Trap Generations in High-k Gate Dielectrics through Systematic RTN Characterizations and Ab initio Calculations,” in Symposia on VLSI Technology, Hawaii, USA, June, 2016.
Other Related Work
[1] J. Wang, J. Niu, Shao Bin, G. Yang, C. Lu, M. Li, Z. Zhou, X. Chuai, J. Chen, N. Lu, B. Huang, Y. Wang, L. Li*, M. Liu*, “A tied Fermi liquid to Luttinger liquid model for nonlinear transport in conducting polymers”, Nature Communications. 12. 10.1038, (2021)
[2] J. Wang, Z. Ji, G. Yang, X. Chuai, F. Liu, Z. Zhou, C. Lu, W. Wei, X. Shi, J. Niu, L. Wang, H. Wang, J. Chen, Nianduan Lu, Chao Jiang*, Ling Li* and M. Liu, “Charge Transfer within the F4 TCNQ-MoS2 van der Waals Interface: Toward Electrical Properties Tuning and Gas Sensing Application,” Adv. Funct. Mater. (2018) 1806244;
[3] X. Zhan, C. Shen, Z. Ji*, J. Chen, H. Fang, F. Guo and J. Zhang, “A Dual-Point technique for the entire ID-VG characterization into subthreshold region under Random Telegraph Noise condition”, IEEE Electron Device Letter, vol.40, 5, pp.674-677, 2019;
[4] Yang, Guanhua & Shao, Yan & Jiebin, Niu & Ma, Xiaolei & Lu, Congyan & Wei, Wei & Xichen, Chuai & Wang, Jiawei & Cao, Jingchen & Huang, Hao & Xu, Guangwei & Shi, Xuewen & Ji, Zhuoyu & Lu, Nianduan & Geng, Di & Qi, Jing & Cao, Yun & Liu, Zhongliu & Liu, Liwei & Liu, Ming. (2020). Possible Luttinger liquid behavior of edge transport in monolayer transition metal dichalcogenide crystals. Nature Communications. 11. 10.1038/s41467-020-14383-0.
[5] H. Hu, Y. Feng, X. Zhan, K. Xi, L. Ji, J. Chen, J. Liu, “Experimental characterizations on TID Radiation Impacts in Charge-trap 3D NAND Flash Memory”, Silicon Nanoelectronics Workshop (SNW), Virtual, June, 2021;
[6] Q. Hu, B. Gao, J. Tang, Z. Hao, P. Yao, Y. Lin, Y. Xi, M. Zhao, “Identifying Relaxation and Random Telegraph Noises in Filamentary Analog RRAM for Neuromorphic Computing”, IEEE Electron Devices Technology and Manufacturing (EDTM) conferences, April 8-11, 2021, Chengdu, China;
[7] M. Xu, B. Gao, F. Xu, W. Wu, J. Tang, J. Chen, H. Qian, “A Compact Model of Analog RRAM Considering Temperature Coefficient for Neural Network Evaluation”, IEEE Electron Devices Technology and Manufacturing (EDTM) conferences, April 8-11, 2021, Chengdu, China;
[8] X. Shi, G. Xu, X. Duan, N. Lu, J. Chen, L. Li, M. Liu, “Analytical model of energy level alignment at metal-organic interface facilitating hole injection,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp.225-228, 2017.
[9] H. Qiu, K. Takeuchi, T. Mizutani, T. Sarya, J. Chen, M. Kobayashi and T. Hitamoto. “Statistical Analyses of Random Telegraph Noise (RTN) Amplitude in Ultra-Narrow (Deep Sub-10nm) Silicon Nanowire Transistors,” in Symposia on VLSI Technology, Kyoto, Japan, June, 2017.
