Low Lattice Mismatch InSe-Se Vertical Van der Waals Heterostructure for High-performance Transistors via Strong Fermi-Level Depinning
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Institution:海洋研究院
Title of Paper:Low Lattice Mismatch InSe-Se Vertical Van der Waals Heterostructure for High-performance Transistors via Strong Fermi-Level Depinning
Journal:Small Methods
Key Words:contact engineering;field-effect transistors;InSe;van der Waals heterostructures
First Author:Jiang, Jianfeng
Document Code:1395241502623404033
Volume:4
Issue:8
Number of Words:20
Translation or Not:No
Date of Publication:2020-08
Release Time:2025-09-22