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个人信息Personal Information
教授 硕士生导师
主要任职：Assistant Professor
性别：女
在职信息：在职
所在单位：计算机科学与技术学院
入职时间：2015-10-23
办公地点：Room 420, N3 Building, Qingdao Campus, Shandong University
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- [41] 蔡晓军 , 鞠雷 , 赵梦莹 , 贾智平 and 王冠. Shared Last-level Cache Management for GPGPUs with Hybrid Main Memory. PROCEEDINGS OF THE 2017 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 25, 2017.
- [42] 张志勇 , 贾智平 , 鞠雷 , 赵梦莹 and 丁宪忠. Unified nvTCAM and sTCAM Architecture for Improving Packet Matching Performance. ACM SIGPLAN NOTICES, 52, 91, 2017.
- [43] 赵梦莹 and 贾智平. State Asymmetry Driven State Remapping in Phase Change Memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36, 27, 2017.
- [44] 赵梦莹. Data re-allocation enabled cache locking for embedded systems. IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC), 2013.
- [45] 赵梦莹. Redesigning Software and Systems for Non-volatile Processors on Self-powered Devices. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016.
- [46] 赵梦莹. Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices. The 51st Annual Design Automation Conference on Design Automation Conference (DAC), 2012.
- [47] 赵梦莹. Compiler Directed Automatic Stack Trimming for Efficient Non-Volatile Processors. Design Automation Conference, 2015.
- [48] 赵梦莹. Migration-aware Loop Retiming for STT-RAM based Hybrid Cache in Embedded Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014.
- [49] 赵梦莹. Profit maximization through process variation aware high level synthesis with speed binning. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013.
- [50] 赵梦莹 and 贾智平. Stack-Size Sensitive On-Chip Memory Backup for Self-Powered Nonvolatile Processors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36, 1804, 2017.
- [51] 贾智平 and 赵梦莹. Multipath Load Balancing in SDN/OSPF Hybrid Network. IFIP International Conference on Network and Parallel Computing, 2016.
- [52] 蔡晓军 , 鞠雷 , 赵梦莹 and 贾智平. Shared Last-level Cache Management for GPGPUs with Hybrid Main Memory. Design, Automation & Test in Europe Conference, 2016.
- [53] 赵梦莹. Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache. roceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems (LCTES), 2012.
- [54] 赵梦莹. WCET-aware re-scheduling register allocation for real-time embedded systems with clustered VLIW architecture. Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems (LCTES), 2012.
- [55] 蔡晓军 , 贾智平 , 鞠雷 and 赵梦莹. A Novel Page Caching Policy for PCM and DRAM of Hybrid Memory Architecture. The 2016 International Conference on Embedded Software and Systems (ICESS2016), 2016.
- [56] 赵梦莹. C3: Cooperative Code Positioning and Cache Locking for WCET Minimization. IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 2015.
- [57] 赵梦莹. Active compensation technique for the thin-film transistor variations and OLED aging of mobile device displays. Proceedings of the International Conference on Computer-Aided Design (ICCAD), 2012.
- [58] 赵梦莹. Mobile devices user - The subscriber and also the publisher of real-time OLED display power management plan. Proceedings of the International Conference on Computer-Aided Design (ICCAD), 2012.
- [59] 赵梦莹. Exploiting parallelism in I/O scheduling for access conflict minimization in flash-based solid state drives. The 30th Symposium on Mass Storage Systems and Technologies (MSST), 2014.
- [60] 赵梦莹. Retention Trimming for Wear Reduction of Flash Memory Storage Systems. The 51st Annual Design Automation Conference on Design Automation Conference (DAC), 2014.