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Degree:Doctor
Status:Employed
School/Department:School of Intergrate Circuit

徐明升

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Gender:Male

Education Level:Postgraduate (Postdoctoral)

Alma Mater:Shandong University

Patents

Current position: Home / Scientific Research / Patents
测量SiC MOSFET沟道近界面陷阱密度的方法
Release Time:2025-06-12 | Hits:

Institution:新一代半导体材料研究院

Type of Patent:Invent

Application Number:202411603552.1

Number of Inventors:5

Service Invention or Not:No

Application Date:2024-11-12

Publication Date:2025-03-07

Authorization Date:2025-03-07