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Bits Mapping in Triple-level-cell (TLC) Charge-trap (CT) 3D NAND Flash Memory and its Applications to IoT Security
Affiliation of Author(s):信息科学与工程学院
First Author:席义方
Document Code:BAEC57095B2F4ABAB9B3E06E8CEADB73
Number of Words:3
Translation or Not:no
Date of Publication:2021-11-24