陈杰智，国家海外青年特聘专家，山东省杰出青年基金获得者，山东大学信息科学与工程学院教授，IEEE高级会员。研究领域主要包括非挥发性存储器可靠性、低功耗纳米器件、新型器件材料设计、存储芯片系统与存算设计。主持了国家科技部重点研发项目课题和国家基金委重点项目等多项国家级/省级/企业的研究项目和课题，与国内外著名大学、研究机构及集成电路企业建立了良好的合作关系。近五年发表了七十余篇高水平SCI/EI检索论文，十七次在微电子集成电路国际顶级会议IEDM/VLSI Symposium上报告研究进展，获得21项美国/日本专利授权和9项中国专利授权。

学术组织任职：

• IEEE IEDM国际电子器件会议技术委员（2016~2017, 2022~2023）

• IEEE IMW国际内存会议科学技术委员（2020~2024）

• IEEE IRPS国际可靠性物理会议技术委员（2019~2020）

• IEEE SNW国际电子器件会议技术委员（2017~2020）

• IEEE IRPS国际可靠性物理会议内存分会主席（2021）

• IEEE EDTM电子器件技术与制造会议半导体器件分会主席（2021~2022）

• 《半导体学报》青年编委（2021~）

代表性学术成果：

• "Temperature-dependent Defect Behaviors in Ferroelectric Hf0.5Zr0.5O2 Thin Film:  Re-wakeup Phenomenon and Underlying Mechanisms,"

  2022 IEDM Tech. Dig., 32.3.1-4;

• "Design-Technology Co-Optimizations (DTCO) for General-Purpose In-Memory Computation Based on 55nm NOR Flash Technology"

  2021 IEDM Tech. Dig., 12.1.1-4; 

•  "In-depth Understanding of Polarization Switching Kinetics in Polycrystalline Hf0.5Zr0.5O2 Ferroelectric Thin Film: A Transition from NLS to KAI,"

  2021 IEDM Tech. Dig., 19.1.1-4;

• "Two-Dimensional Silicon Atomic Layer Field-Effect Transistors: Electronic Property, Metal-Semiconductor Contact, and Device Performance,"

  2021 IEDM Tech. Dig., 27.2.1-4;

• “Deep Insights into the Failure Mechanisms in Field-cycled Ferroelectric Hf0.5Zr0.5O2 Thin Film: TDDB Characterizations and First-Principles Calculations”

  2020 IEDM Tech. Dig., 39.6.1-4;

•  “Cold Source Engineering towards Sub-60mV/dec p-Type Field-effect-transistors (pFETs): Materials, Structures, and Doping Optimizations”

  2020 IEDM Tech. Dig., 22.4.1-4;

•  “Computational Design of Silicon Contacts on 2D Transition-Metal Dichalcogenides: The Roles of Crystalline Orientation, Doping Level, Passivation and Interfacial layer"

  2018 IEDM Tech. Dig., 21.2.1-4;

•  “A low-power and high-speed True Random Number Generator using generated RTN,”

  2018 Symposia on VLSI Technology, pp.95-96;

• “Comprehensive Investigations on Charge Diffusion Physics in SiN-based 3D NAND Flash Memory through Systematical Ab initio Calculations"

  2017 IEDM Tech. Dig., 4.5.1-4;

• “Deep Insight into Process-induced Pre-existing Traps and PBTI Stress-induced Trap Generations in High-k Gate Dielectrics through Systematic RTN Characterizations and Ab initio Calculations,”

  2016 Symposia on VLSI Technology;

• “Further Investigations on Traps Stabilities in Random Telegraph Signal Noise and the Application to a Novel Concept Physical Unclonable Function (PUF) with Robust Reliabilities,”

  2015 Symposia on VLSI Technology;

• “Further Understandings on Random Telegraph Signal Noise through Comprehensive Studies on Large Time Constant Variations and its Strong Correlations to Thermal Activation Energies,”

  2014 Symposia on VLSI Technology;

•  “Understanding of Channel Doping Concentration Impacts on Random Telegraph Signal Noise and Successful Noise Suppression from Strain Induced Mobility Enhancement,”

  2013 Symposia on VLSI Technology;

• “Comprehensive Investigations on Neutral and Attractive Traps in Random Telegraph Signal Noise Phenomena using (100)- and (110)-Orientated CMOSFETs,” 

  2012 Symposia on VLSI Technology;

• “Mobility enhancement over universal mobility in (100) silicon nanowire gate-all-around MOSFETs with width and height of less than 10nm range,”

  2010 Symposia on VLSI Technology;

•  “High Hole Mobility in Multiple Silicon Nanowire Gate-All-Around pMOSFETs on (110) SOI,”

  2009 Symposia on VLSI Technology;

• ”Experimental Study of Mobility in [110]- and [100]-Directed Multiple Silicon Nanowire GAA MOSFETs on (100) SOI,”

  2008 Symposia on VLSI Technology;

•  “Electron Mobility in Multiple Silicon Nanowires GAA nMOSFETs on (110) and (100) SOI at Room and Low Temperature,”

  2008 IEDM Tech. Dig., p.761-764