针对微电子和集成电路领域在后摩尔时代的关键问题，研究“More Moore”技术中高可靠性器件的协同性设计策略，解决“More Moore”跨向“Beyond CMOS”所面临的材料工艺融合问题。目前，课题组正在开展CMOS晶体管器件、非挥发性半导体存储器、新型存算融合与三维集成等三个研究方向，通过结合材料计算、器件制备、架构设计，以及芯片测试等多种研究手段研究高可靠性新型纳米器件及半导体存储器。

   Publications in Journals  

1. Y. Feng, J. Chen*, et al., "A Novel Array Programming Scheme for Large Matrix Processing in Flash-Based Computing-in-Memory (CIM) With Ultrahigh Bit Density," in IEEE Transactions on Electron Devices, doi: 10.1109/TED.2022.3227529

2. X. Li, W. Wei, J. Wu, L. Tai, X. Zhan, W. Zhang, M. Tang, G. Zhao, X. Hao, J. Chai, X. Wang, M. Kobayashi, J. Chen*, “Experimental investigations on ferroelectric dielectric breakdown in sub-10 nm Hf0.5Zr0.5O2 film through comprehensive TDDB characterization.” Japanese Journal of Applied Physics 61.10 (2022): 101002;

3. G. Zhao, S. Wu, X. Zhan, M. Tang, W. Wei, L. Tai, J. Wu, J. Chai, H. Xu, W. Wang, J. Chen*, "Design-Technology Co-optimizations for Symmetric Linear Synapse Behaviors in Ferroelectric FET based Neuromorphic Computing", IEEE Transactions on Nanotechnology, 2022, 21: 747-751;

4. M. Tang, X. Zhan*, S. Wu, M. Bai, Y. Feng, G. Zhao, J. Wu, J. Chai, H. Xu, X. Wang, J. Chen*, "A Compact Fully Ferroelectric FETs Reservoir Computing Network with Sub-100ns Operating Speed." IEEE Electron Device Letters 43.9 (2022):1555-1558;

5. Y. Feng, J. Wu, X. Zhan, J. Liu*, Z. Sun, J. Zhang, M. Kobayashi, J. Chen, "A Novel Encrypted Computing-in-Memory (eCIM) by Implementing Random Telegraph Noise (RTN) as Keys Based on 55 nm NOR Flash Technology." IEEE Electron Device Letters 43.9 (2022): 1455-1458; 

6. D. Zhang, H. Wang, Y. Feng, X. Wang, G. Liu, K. Han, X. Gong*, J. Liu*, X. Zhan, J. Chen*,  "Fast Fourier Transform (FFT) Using Flash Arrays for Noise Signal Processing," IEEE Electron Device Letters 43.8 (2022): 1207-1210;

7. B. Chen, S. Wu, X. Yu, M. Tang, G. Zhao, L. Tai, X. Zhan*, J. Chen*, "Ferroelectricity induced double-direction conductance modulation in HfxZr1-xO2 capacitors", Nanotechnology, 2022, 33: 495201; 

8. P. Sang, Q. Wang, W. Wei,  Y. Li, C. Li, J. Chen*, "Extending the Scaling Limit of Silicon Channel Transistors Through hhk-Silicene Monolayer: A Computational Study," IEEE Transactions on Electron Devices, 2022, 69(6): 3494-3498;

9. B. Chen, S. Wu, X. Yu, M. Tang, G. Zhao, L. Tai, X. Zhan*, J. Chen*, "Ferroelectricity induced double-direction conductance modulation in HfxZr1-xO2 capacitors", Nanotechnology, 2022, 33: 495201;

10. W. Wei, G. Zhao, X. Zhan, W. Zhang, P. Sang, Q. Wang, L. Tai, Q. Luo, Y. Li, C. Li and J. Chen*, "Switching pathway-dependent strain-effects on the ferroelectric properties and structural deformations in orthorhombic HfO2." Journal of Applied Physics, 131.15 (2022): 154101;

11. P. Sang, Q. Wang, W. Wei, L. Tai, X. Zhan, Y. Li and J. Chen*, "Two-dimensional silicon atomic layer field-effect transistors: Electronic property, metal-semiconductor contact, and device performance," IEEE Transactions on Electron Devices, 69.4 (2022), 2173-2179;

12. Q. Wang, P. Sang, W. Wei, Y. Li, J. Chen, “Functionalized MoS2 Nanoribbons for Intrinsic Cold-Source Transistors: A Computational Study”, ACS Applied Nano Materials, 2022 5 (1), 1178-1184;

13. M. Tang, X. Zhan* and J. Chen*, "Improved Crossbar Array Architecture for Compensating Interconnection Resistance: A Ferroelectric HZO-based Synapse Case,"  IEEE Journal of the Electron Devices Society 10 (2022): 192-196;

14. M. Jia, Y. Kong, X. Zhan, M. Zhang, F. Wu, J. Chen, "Optimal Program-Read Schemes Towards Highly Reliable Open Block Operations in 3D Charge-trap NAND Flash Memory," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022, 41(11): 4797-4807; 

15. X. Zhan, J. Chen*, Z. Ji*, "Insights of VG-dependent threshold voltage fluctuations from dual-point random telegraph noise characterization in nanoscale transistors," in Science China Information Sciences, 2022, 65: 189405；

16. D. Zhang, H. Wang, Y. Feng, X. Zhan, J. Chen*, J. Liu*, M. Liu, "Implementation of Image Compression by Using High-Precision In-Memory Computing Scheme Based on NOR Flash Memory", IEEE Electron Device Letters, 42(11), p.1603, 2021;

17. X. Ma, Y. Liu, L. Zeng, J. Chen*, R. Wang*, L. Wang, Y. Wu, and X. Jiang*,” Defects Induced Charge Trapping/Detrapping and Hysteresis Phenomenon in MoS2 Field-Effect Transistors: Mechanism Revealed by Anharmonic Marcus Charge Transfer Theory”, ACS Applied Materials & Interfaces, 2022, 14 (1), 2185-2193;

18. F. Chen, B. Chen, H. Lin, Y. Kong, X. Liu, X. Zhan, J. Chen*, "Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories", Micromachines, 12, 1152, 2021;

19. P. Sang, Q. Wang, W. Wei, F. Wang, Y. Li*, J. Chen*, "Semiconducting Silicene: A Two-Dimensional Silicon Allotrope with Hybrid Honeycomb-Kagome Lattice"，ACS Materials Lett. 3, 8, p.1181, 2021 (cover);

20. Q. Wang, P. Sang, F. Wang, W. Wei, J. Chen*, "Tunneling Junction as Cold Source: Toward Steep-Slope Field-Effect Transistors Based on Monolayer MoS2", IEEE Transactions on Electron Devices, 68(9), p.4758, 2021;

21. Q. Wang, P. Sang, F. Wang, W. Wei, Y. Li, J. Chen*, "Strain engineered C31 field-effect-transistors: a new strategy to break 60mV/decade by using electron injection from intrinsic isolated states", APEX, 14, p.074003, 2021;

22. X. Zhan, G. Zhao, X. Yu, B. Chen, J. Chen*, “Digital and analog functionality in monolayer AlOx-based memristors with various oxidizer sources”, Nanotechnology, 35LT01, 2021;

23. F. Wang, Y. Li, X. Ma, J. Chen*, “Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory”, IEEE Access, 9, 47391, 2021;

24. Z. Zhou, J. Wang*, J. Chen*, C. Jiang, L. Li*, M. Liu, “Directly probing the charge transport in initial molecular layers of organic polycrystalline field effect transistors”, Journal of Materials Chemistry C, 9, 649-656, 2021;

25. Y. Feng, F. Wang, X. Zhan, Y. Li, J. Chen*, “Flash Memory based Computing-in-memory system to Solve Partial Differential Equations”, Sci. China Inf. Sci., 64, 169401, 2021;

26.  P. Sang, X. Ma, Q. Wang, W. Wei, F. Wang, J. Wu, X Zhan, Y Li*, J. Chen*, “Toward high-performance monolayer graphdiyne transistor: Strain engineering matters”, Applied Surface Science, 536, p.147836, Jan. 2021;

27. Y. Kong, M. Zhang, X. Zhan, R. Cao, J. Chen*, “Retention Correlated Read Disturb Errors in 3-D Charge Trap NAND Flash Memory: Observations, Analysis, and Solutions”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 11, pp. 4042-4051, Nov. 2020;

28. F. Wang, Y. Feng, X. Zhan, B. Chen*, J. Chen*, “Implementation of Data Search in Multi-level NAND Flash Memory by Complementary Storage Scheme”, IEEE Electron Device Letter, 41, 8, 1189, Aug. 2020;

29. F. Lu, Q. Qin, Y. Li*, J. Chen*, “Computational design of molecular transistor with van der Waals gating”, Applied Physics Express, 13, 085002, Aug. 2020;

30. X. Zhan, Y. Xi, Q, Wang, W. Zhang, Z. Ji, and J. Chen*, “Dual-Point Technique for Multi-Trap RTN Signal Extraction”, IEEE Access, 8, 88141, 2020;

31. F. Wang, R. Cao, Y. Kong, X. Ma, X. Zhan, Y. Li, J. Chen*, “Lateral Charge Migration Induced Abnormal Read Disturb in 3D Charge-Trapping NAND Flash Memory”, Applied Physics Express, 13, 054002, May. 2020;

32. Y. Li*, Y. Yi, B. Cui, J. Chen*, “Two-dimensional electronic and charge-transport properties of a monolayer organic crystal: Impacts of the collinear transfer-integral correlations”, Organic Electronics 78, 105609, 2020;

33. F. Wang, J. Wu, Y. Li, R. Cao, J. Chen*, “Metallic doping: A new strategy for suppressing shallow-trap centers in vertically stacked charge-trapping flash memories”, Applied Physics Express, 13, 044001, Apr. 2020;

34. X. Ma, F. Wang, W. Wei, J. Wu, X. Zhan, Y. Li, J. Chen*, “Impacts of Extra Charges on Trap Level Modulations at cSi/aSiO2 Interface: Correlations to Leakage Current Recovery in Oxide Dielectric”, J. Phys. D: Appl. Phys., 53, 245103, Jun. 2020;

35. X. Ma, X. Jiang, Yuan Li, J. Chen*, “Schottky-barrier modulation at germanium/monolayer MoS2 heterojunction interface: the roles of passivation and interfacial layer”, Applied Physics Express,13, 021004, 2020

36. X. Ma, Y. Gong, J. Wu, Y. Li, J. Chen*, “Impacts of atomistic surface roughness on electronic transport in n-type and p-type MoS2 field-effect transistors”, Jpn. J. Appl. Phys. 58 110905, 2019;

37. W. Wei, X. Ma, J. Wu, F. Wang, X. Zhan, Y. Li, J. Chen*, “Spontaneous polarization enhancement in ferroelectric Hf0.5Zr0.5O2 using atomic oxygen defects engineering: an ab initio study”, Appl. Phy. Lett., 115, 092905, 2019;

38. J. Wu, J. Chen*, X. Jiang*, “Multiscale simulation of lateral charge loss in Si3N4 3D NAND flash based on density functional theory”, J. Phys. D: Appl. Phys. 52, 395103, 2019;

39. J. Wu, J. Chen*, X. Jiang*, “Atomistic Study of Lateral Charge Diffusion Degradation During Program/Erase Cycling in 3-D NAND Flash Memory”, IEEE Journal of the Electron Devices Society, vol.7,1, pp.626-631, 2019;

40. J. Wu, X. Ma, J. Chen*, X. Jiang*, “Defects coupling impacts on mono-layer WSe2 tunneling field-effect transistors”, Applied Physics Express,12, 034001, 2019;

41. X. Zhan, M. Hou, F. Ma, Y. Su, J. Chen*, H. Xu*, “Room temperature crystallization of amorphous silicon film by ultrashort femtosecond laser pulses”, Optics and Laser Technology 112 (2019), pp.363-367;

42. Z. Fan, J. Chen* and X. Jiang*, “Electrical Contacts and Tunable Rectifications in Monolayer GeSe-Metal Junctions,” Journal of Physics D: Appl. Phys. 51 (2018) 335104;

43. J. Lu, Z. Fan*, J. Gong*, J. Chen*, H. ManduLa, Y. Zhang, S. Yang and X. Jiang, “Enhancement of tunneling current in monolayer phosphorene tunnel field effect transistors by surface defects,” Physical Chemistry Chemical Physics, 20, pp.5699~5707, 201;

44. J. Wu, Z. Fan, J. Chen*, X. Jiang*, “Atomic defects in monolayer WSe2 tunneling FETs studied by systematic ab initio calculations,” Applied Physics Express,11, 054001, 2018.

International Conferences

1. X. Li, J. Wu*, L. Tai, W. Wei, P. Sang, Y. Feng, B. Chen, G. Zhao, X. Zhan, X. Wang. M. Kobayashi, J. Chen*, "Temperature-dependent Defect Behaviors in Ferroelectric Hf0.5Zr0.5O2 Thin Film:  Re-wakeup Phenomenon and Underlying Mechanisms," IEDM Tech. Dig., 32.3.1-4, 2022, San Francisco, USA;

2. K. Xie, P. Guo, F. Chen, B. Chen, X. Fnag, J. Wu, X. Zhan, J. Chen*, "Large Suppression to Lateral Charge Migration (LCM) Related Error Bits in Charge-Trap TLC 3D NAND Flash," IEEE International conference on integrated circuits technologies and applications (ICTA), virtual, November, 2022;

3. X. Fang, M. Zhang, Y. Guo, F. Chen, B. Chen, X. Zhan, J. Wu, F. Wu and J. Chen*, High-Precision Short-Term Lifetime Prediction in TLC 3D NAND Flash Memory as Hot-data Storage, ESWEEK, 2022;

4. G. Zhao, et al.,“Suppressing Interfacial Layer Degradation in Hf0.5Zr0.5O2-based FeFETs Using a Pre-erase Strategy during Program/Erase Cycling,” Silicon Nanoelectronics Workshop (SNW), virtual, June, 2022;

5. H. Lin, et al.,“Optimal Read Voltages of Retention-after-Cycling in Triple-level-cell (TLC) 3D NAND Flash Memory and its High-precision Modeling Method”, Silicon Nanoelectronics Workshop (SNW), virtual, June, 2022;

6. W. Zhang, B. Chen, W. Wei, L. Tai, X. Zhan, F. Wang, J. Chen*, "Experimental observations on C-V measurement caused performance degradations in Hf0.5Zr0.5O2 ferroelectric film," 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), pp.378-380, 2022

7. B. Chen, Y. Kong, X. Fang, X. Zhan, and J. Chen*, "High-to-Low Flippling (HLF) Coding Strategy in Triple-levell-cell (TLC) 3D NAND Flash Memory to Construct  Reliable Image Storages," 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), pp.336-368, 2022；

8. F. Yang, B. Chen, J. Liu, Z. Sun, H. Hu, J. Zhang, X. Zhan, J. Chen*, "Design-Technology Co-Optimizations (DTCO) for General-Purpose In-Memory Computation Based on 55nm NOR Flash Technology", IEDM Tech. Dig., 12.1.1-4, 2021, San Francisco, USA; 

9. W. Wei, W. Zhang, L. Tai, G. Zhao, P. Sang, Q.Wang, F. Chen, M.Tang, Y. Feng, X. Zhan, Q. Luo, Y. Li and J. Chen*, "In-depth Understanding of Polarization Switching Kinetics in Polycrystalline Hf0.5Zr0.5O2 Ferroelectric Thin Film: A Transition from NLS to KAI," IEDM Tech. Dig., 19.1.1-4, 2021, San Francisco, USA;

10. P. Sang, Q. Wang, W. Wei, L. Tai, X. Zhan, Y. Li, J. Chen*, "Two-Dimensional Silicon Atomic Layer Field-Effect Transistors: Electronic Property, Metal-Semiconductor Contact, and Device Performance," IEDM Tech. Dig., 27.2.1-4, 2021, San Francisco, USA;

11. J. Chen* (invited), "Reliability Issues in Charge-Trap 3D NAND Flash Memories and Optimization Strategies", IEEE International Conference on ASIC (ASICON), virtual, November,  2021; 

12. Y. Xi, X. Fang, Y. Kong, Y. Guo, H. Lin, X. Zhan, J. Chen*, "Error Bits Mapping in Triple-level-cell (TLC) Charge-trap (CT) 3D NAND Flash Memory and its Applications to IoT Security", IEEE International conference on integrated circuits technologies and applications (ICTA), TH1C, virtual, November, 2021 (Best Paper Award);

13. Q. Jin, L. Cui, X. Zhan, J. Liu, J. Chen*, “Variations of Bias Dependent Timing Constants and Its Implication on Trap Positions and Energy Levels by the Hidden Markov Model”, Silicon Nanoelectronics Workshop (SNW), virtual, June, 2021;

14. F. Lu, Y. Li*, J. Chen*, “Electronic Transport Across the Grain Boundary of Poly-Si Channel In 3D NAND Flash Memory: A Theoretical Perspective”, Silicon Nanoelectronics Workshop (SNW), virtual, June, 2021;

15. F. Wang, X. Ma, W. Wei, P. Sang, Q. Wang, W. Zhang, Y. Li, J. Chen*, “Sub-3nm Transition-Metal Dichalcogenides FETs: Theoretical Insights into the Impacts of Layer Numbers and Channel Lengths”, IEEE Electron Devices Technology and Manufacturing (EDTM) conferences, April 8-11, 2021, Chengdu, China;

16. X. Fang, Y. Kong, Y. Guo, M. Jia, X. Zhan, Y. Li, J. Chen*, “Impacts of Operation Intervals on Program Disturb in 3D Charge-trapping Triple-level-cell (TLC) NAND Flash Memory”, IEEE Electron Devices Technology and Manufacturing (EDTM) conferences, April 8-11, 2021, Chengdu, China;

17. W. Wei, W. Zhang, F. Wang, X. Ma, Q. Wang, P. Sang, X. Zhan, Y. Li, L. Tai, Q. Luo, H. Lv, J. Chen*,  “Deep Insights into the Failure Mechanisms in Field-cycled Ferroelectric Hf0.5Zr0.5O2 Thin Film: TDDB Characterizations and First-Principles Calculations”, IEDM Tech. Dig., 39.6.1-39.6.4, 2020;

18. Q. Wang, P. Sang, X. Ma, Y. Li, J. Chen*, “Cold Source Engineering towards Sub-60mV/dec p-Type Field-effect-transistors (pFETs): Materials, Structures, and Doping Optimizations”, IEDM Tech. Dig., 22. 4. 1-22. 4. 4, 2020;

19. F. Wang, X. Zhan, Y. Li, J. Chen*, “Impacts of Poly-Si Channel on Cell Variations in Vertical Scaled Charge-trap (CT) 3D NAND Flash Memory”, the International Conference on Solid-State and Integrated Circuit Technology (ICSICT), virtual, Nov.3-6, 2020;

20. X. Peng, F. Wang, Y. Kong, M. Jia, X. Zhan, Y. Li, J. Chen*, “Impacts of Lateral Charge Migration on Data Retention and Read Disturb in 3D Charge-trap NAND Flash Memory”, the International Conference on Solid-State and Integrated Circuit Technology (ICSICT), virtual, Nov.3-6, 2020;

21. Y. Kong, X. Peng, F. Wang, M. Jia, X. Zhan, Y. Li, J. Chen*, “Comprehensive Investigations on Data Pattern Dependences in Charge-trap (CT) 3D NAND Flash Memory”, the International Conference on Solid-State and Integrated Circuit Technology (ICSICT), virtual, Nov.3-6, 2020;

22. J. Chen (invited), “Read Disturbs in Triple-Level-Cell 3D Charge-trap NAND Flash Memory”, the International Conference on Solid-State and Integrated Circuit Technology (ICSICT), virtual, Nov.3-6, 2020;

23. Q. Qin, F. Wang, X. Zhan, Y. Li, J. Chen*, “TID Radiation Impacts on Charge-trapping Macaroni 3D NAND Flash Memory”, accepted by IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), virtual, July, 2020;

24. Y. Feng, J. Chen*, “Flash Memory based Computing-In-Memory to Solve Time-dependent Partial Differential Equations”, Silicon Nanoelectronics Workshop (SNW), virtual, June, 2020;

25. Q. Wang, P. Sang, Y. Li, W. Wei, F. Wang, J. Chen*, “Biaxial Tensile Strain Impacts on Monolayer WSe2 Tunneling Field-effect-transistor (TFET)”, Silicon Nanoelectronics Workshop (SNW), virtual, June, 2020;

26. Y. Li, Q. Wang, X. Zhan, M. Jia, R. Cao, J. Chen*, “a Novel quasi-SLC(qSLC) Program/Erase Scheme in Ultra-Densified Charge-trapping 3D NAND Flash Memory to Enhance System Level Performance”, Silicon Nanoelectronics Workshop (SNW), virtual, June, 2020;

27. X. Ma, R. Cao, F. Wang, X. Zhan, J. Chen*, “Charge-assisted Recovery and Degradation in Charge-trapping 3D NAND Flash Memory, Experimental Evidences and Theoretical Perspectives”, Silicon Nanoelectronics Workshop (SNW), virtual, June, 2020;

28. F. Wang, X. Ma, J. Wu, J. Chen*, X. Jiang*, “Atomistic Study of Transport Characteristics in Sub-1nm Ultra-narrow Molybdenum Disulfide (MoS2) Nanoribbon Field Effect Transistors”, Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, June, 2019;

29. J. Wu, J. Chen*, X. Jiang*, “Excess Charge Effects on Semiconductor-metal Phase Transition in Mono-layer MoTe2”, Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, June, 2019;

30. R. Cao, J. Wu, W. Yang, J. Chen*, X. Jiang*, “Program/Erase Cycling Enhanced Lateral Charge Diffusion in Triple-level Cell Charge-trapping 3D NAND Flash Memory”, IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2019;

31. X. Ma, Y. Liu, L. Wang, Y. En, J. Chen*, X. Jiang*, “Scaling behavior of state-to-state coupling during hole trapping at Si/SiO2”, IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2019;

32. X. Ma, Z. Fan, J. Wu, X. Jiang*, J. Chen*, “Computational Design of Silicon Contacts on 2D Transition-Metal Dichalcogenides: The Roles of Crystalline Orientation, Doping Level, Passivation and Interfacial layer", IEDM Tech. Dig., San Francisco, CA, USA, p.21.2.1, 2018;

33. X, Zhan, F. Ma, J. Chen*, Y. Li and H. Xu*, “Crystallizing amorphous silicon film by using femtosecond laser pulses,” 2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), pp.84-85, November 21- 23, 2018, Beijing, China;

34. W. Yang, Y. Li, B. Wang, H. Qian and J. Chen*, “Positive Bias Temperature Instabilities in Vertical Gate-all-around poly-Si Nanowire Field-effect Transistor,” 2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), pp.175-176, November 21- 23, 2018, Beijing, China;

35. J. Chen (invited), “On the Reliability of Charge-Trap (CT) Type Three-dimensional (3D) NAND Flash Memory,” the 14th International Conference on Solid-State and Integrated Circuit Technology, October 31-November 3, 2018, Qingdao, China;

36. R. Cao, J. Wu, W. Yang, Y. Li, J. Chen*, “Error Bit Distributions in Triple-level Cell Three-dimensional (3D) NAND Flash Memory,” the 14th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), October 31- November 3, 2018, Qingdao, China;

37. F. Ma, X. Zhan, Y. Li, J. Chen*, “Numerical Simulations on Nanosecond Pulse Laser Annealing in Vertical Polycrystalline Si Macaroni Channel,” the International Conference on Solid-State and Integrated Circuit Technology (ICSICT), October 31- November 3, 2018, Qingdao, China;

38. J. Brown, R. Gao, J. Crowford, J. Wu, Z. Ji*, J. Chen*, J. Zhang, B. Zhou, B. Zhou, Q. Shi, W. Zhang, “A low-power and high-speed True Random Number Generator using generated RTN,” Symposia on VLSI Technology, pp.95-96, Hawaii, USA, June, 2018;

39. J. Wu, X. Ma, J. Chen*, X. Jiang*, “Se Vacancy Defects Coupling Effects in Mono-layer WSe2 Tunnel FETs”, Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, June, 2018;

40. X. Ma, Z. Fan, J. Wu, J. Chen*, X. Jiang*, “Channel Bending Effects on On/Off Currents in Mono-Layer MoS2 FETs”, Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, June, 2018;

41. W. Yang, J. Zhao, H. Cao, S. Chiu, J. Chen*, “Oxide-Nitride-Oxide(ONO) Inter-poly Dielectric (IPD) Scaling Impacts on Data Retention Characteristics in NAND Flash Memories”, Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, June, 2018;

42. J. Wu, D. Han, W. Yang, S. Chen, X. Jiang*, J. Chen*, “Comprehensive Investigations on Charge Diffusion Physics in SiN-based 3D NAND Flash Memory through Systematical Ab initio Calculations", IEDM Tech. Dig., San Francisco, CA, USA, p.4.5.1-4.5.4, 2017.

43. J. Chen*, J. Wu, X. Jiang, (invited) “Impacts of Traps on Nano Scale Device Performance, Reliability, and Novel Applications”, invited talk, in International Microprocesses and Nanotechnology Conference, JeJu, Korea, November, 2017;

44. J. Wu, Z. Fan, J. Chen*, X. Jiang*, “A Study on W Vacancy Defect in Mono-layer Transition-Metal Dichalcogenide (TMD) TFETs through Systematic Ab initio Calculations”, Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, June, 2017;

45. J. Chen*, Y. Nakasaki and Y. Mitani. “Deep Insight into Process-induced Pre-existing Traps and PBTI Stress-induced Trap Generations in High-k Gate Dielectrics through Systematic RTN Characterizations and Ab initio Calculations,” Symposia on VLSI Technology, Hawaii, USA, June, 2016.

Other Related Work

1. R. Mao, B. Wen, M. Jiang, J. Chen and C. Li, "Experimentally-Validated Crossbar Model for Defect-Aware Training of Neural Networks." IEEE Transactions on Circuits and Systems II: Express Briefs 69.5 (2022): 2468-2472;

2. J. Wang, J. Niu, S. Bin, G. Yang, C. Lu, M. Li, Z. Zhou, X. Chuai, J. Chen, N. Lu, B. Huang, Y. Wang, L. Li*, M. Liu*, “A tied Fermi liquid to Luttinger liquid model for nonlinear transport in conducting polymers”, Nature Communications. 12. 10.1038, (2021);

3. M. Xu; B. Gao*; F. Xu; W. Wu; J. Tang; J. Chen; H. Qian, "A Compact Model of Analog RRAM Considering Temperature Coefficient for Neural Network Evaluation",   IEEE Electron Devices Technology and Manufacturing (EDTM) conferences, April 8-11, 2021, Chengdu, China;

4. N. Lu*, S. Ma, J. Chen, Q. Zhou, L. Li, M. Liu, "A first-principles study of the interface property in oxide-based RRAM", IEEE Electron Devices Technology and Manufacturing (EDTM) conferences, April 8-11, 2021, Chengdu, China;

5. S. Yang, B. Gao*, F. Xu, Q. Hu, J. Tang, J. Chen, H. Qian, "Oxygen Vacancy Formation Accompanied by Hf Oligomer in Amorphous-HfOx-Bascd RRAM: A First Principles Study",  IEEE Electron Devices Technology and Manufacturing (EDTM) conferences, April 8-11, 2021, Chengdu, China;

6. Q. Hu, B. Gao, J. Tang, Z. Hao, P. Yao, Y. Lin, Y. Xi, M. Zhao, J. Chen, H. Qian, H. Wu, "Identifying relaxation and random telegraph noises in filamentary analog RRAM for neuromorphic computing", IEEE Electron Devices Technology and Manufacturing (EDTM) conferences, April 8-11, 2021, Chengdu, China;
   

7. J. Wang, Z. Ji, G. Yang, X. Chuai, F. Liu, Z. Zhou, C. Lu, W. Wei, X. Shi, J. Niu, L. Wang, H. Wang, J. Chen, N. Lu, C. Jiang*, L. Li* and M. Liu, “Charge Transfer within the F4 TCNQ-MoS2 van der Waals Interface: Toward Electrical Properties Tuning and Gas Sensing Application,” Adv. Funct. Mater. (2018) 1806244;

8. X. Zhan, C. Shen, Z. Ji*, J. Chen, H. Fang, F. Guo and J. Zhang, “A Dual-Point technique for the entire ID-VG characterization into subthreshold region under Random Telegraph Noise condition”, IEEE Electron Device Letter, vol.40, 5, pp.674-677, 2019;

9. H. Hu, Y. Feng, X. Zhan, K. Xi, L. Ji, J. Chen, J. Liu, “Experimental characterizations on TID Radiation Impacts in Charge-trap 3D NAND Flash Memory”, Silicon Nanoelectronics Workshop (SNW), Virtual, June, 2021;

10. M. Xu, B. Gao, F. Xu, W. Wu, J. Tang, J. Chen, H. Qian, “A Compact Model of Analog RRAM Considering Temperature Coefficient for Neural Network Evaluation”, IEEE Electron Devices Technology and Manufacturing (EDTM) conferences, April 8-11, 2021, Chengdu, China;

11. X. Shi, G. Xu, X. Duan, N. Lu, J. Chen, L. Li, M. Liu, “Analytical model of energy level alignment at metal-organic interface facilitating hole injection,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp.225-228, 2017.

12. H. Qiu, K. Takeuchi, T. Mizutani, T. Sarya, J. Chen, M. Kobayashi and T. Hitamoto. “Statistical Analyses of Random Telegraph Noise (RTN) Amplitude in Ultra-Narrow (Deep Sub-10nm) Silicon Nanowire Transistors,” in Symposia on VLSI Technology, Kyoto, Japan, June, 2017.