山东大学教师主页辛倩 Paper Publications Home

辛倩

Professor
Supervisor of Doctorate Candidates
Supervisor of Master's Candidates

Gender:Female
Alma Mater:山东大学
Education Level:With Certificate of Graduation for Doctorate Study
Degree:Doctor
Status:Employed
School/Department:集成电路学院
Date of Employment:2012-09-14
College: School of Integrated Circuits,Shandong University
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Current position: Home >> Scientific Research >> Paper Publications

Paper Publications

2022-12
[1] . A High Responsivity and Photosensitivity Self-Powered UV Photodetector Constructed by the CuZnS/Ga2O3 Heterojunction. 先进材料表面Advanced Materials Interfaces, 2202130, 2022.
2025-03
[2] 郑帅英. Enhancement in Performance and Reliability of Fully Transparent a-IGZO Top-Gate Thin-Film Transistors by a Two-Step Annealing Treatment. Nanomaterials, 15, 460, 2025.
2023-09
[3] 颜世琪. Ga<sub>2</sub>O<sub>3</sub> Schottky Avalanche Solar-Blind Photodiode with High Responsivity and Photo-to-Dark Current Ratio. Advanced Electronic Materials, 2023.
2024-11
[4] 姜江一鸣. Zr-Doping Strategy of High-Quality Cu2O/β-Ga2O3 Heterojunction for Ultrahigh-Performance Solar-Blind Ultraviolet Photodetection. ACS Applied Materials & Interfaces, 2024.
2024-06
[5] 殷雪梅. Electrolyte-Gated Amorphous IGZO Transistors with Extended Gates for Prostate-Specific Antigen Detection. LAB ON A CHIP, 2024.
2022-01
[6] 董世林. Interfacial thermal transport of graphene/β-Ga2O3 heterojunctions: a molecular dynamics study with a self-consistent interatomic potential. Physical chemistry chemical physics, 24, 12837-12848, 2022.
2024-04
[7] 郑帅英. Post-annealing effect of low temperature atomic layer deposited Al2O3 on the top gate IGZO TFT. NANOTECHNOLOGY, 35, 155203, 2024.
2024-04
[8] 郑帅英. Post-annealing effect of low temperature atomic layer deposited Al2O3 on the top gate IGZO TFT. NANOTECHNOLOGY, 35, 2024.
2023-11
[9] 王名扬. Performance enhancement of solution-processed p-type CuI TFTs by self-assembled monolayer treatment. 638, 2023.
2018-03
[10] . Amorphous-InGaZnO Thin-Film Transistors Operating Beyond 1 GHz Achieved by Optimizing the Channel and Gate Dimensions. IEEE Transactions on Electron Devices, 1377, 2018.

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